Conventional electrically programmable read-only memory (EPROM) cells typically have control gate members that overlie the top or the top and sides of floating gates. When a control gate member overlies only the top of the floating gate, the capacitive coupling between a floating gate and control gate member typically does not exceed about 50%. When a control gate member lies adjacent to the top and sides of the floating gate, the capacitive coupling between a floating gate and control gate member may increase to about 70%. To reduce programming and erasing voltages, a higher capacitive coupling is required. This feature makes the device more suitable for low voltage nonvolatile memory applications.
An attempt to further increase capacitive coupling may include the use of multiple layers to form a control gate that lies adjacent to the top, sides, and part of the bottom of the control gate layer. Two depositing and two patterning steps may be required just to form the control gate. Further, the intergate dielectric layer (between the control gate member and the floating gate) may include two distinct regions and require three steps to be formed. For example, one region of the intergate dielectric layer may have one thickness between the bottom of the floating gate and an underlying portion of the control gate member, and the other region of the intergate dielectric layer may have a different thickness between the top of the floating gate and an overlying portion of the control gate member. Extra processing steps typically lower yield, increase cycle time, and are generally undesired.